Lab 3:

In The 3rd lab, you will be designing a Traffic Light Controller (FSM) in Verilog.
Consider the following variation on the classical traffic light controller. The intersection is shown in Figure 1.
A Street runs north-south, B Street runs east-west, and C Street enters the intersection from the southeast. A Street is quite busy, and it is frequently difficult for cars heading south on A to make the left turn onto either B or C. In addition, cars rarely enter the intersection from C Street. Design a traffic light state diagram for this three-way intersection to the following specifications:
There are five sets of traffic lights, facing cars coming from A north, A south, B east, B west, and C southeast, respectively.
The red, yellow, and green lights facing cars from A north are augmented with a left turn arrow that can be lit up as either green or yellow or not lit up at all.
The normal sequencing of lights facing the cars coming from A north is arrow green, arrow yellow, traffic light green, traffic light yellow, traffic light red, and repeat. In other words, the left arrow light is illuminated in every complete cycle of the lights.However, it should be possible for traffic going from north to south on A Street to cross the intersection even when the left turn arrow is illuminated. Therefore, the traffic light green should also be illuminated while the turn arrow is lit up.
Cars traveling from south to north on A Street (and all directions on B and C Streets) must see a red light while the left turn arrow is illuminated for the traffic heading south.
A car sensor C is embedded in C Street to detect whether a car is waiting to enter the intersection from the southeast.
A timer generates a long interval signal TL and a short interval signal TS when set by an ST signal.
Red and green lights are lit up for at least a TL unit of time. Yellow lights, the green arrow, and the yellow arrow are lit up for exactly a TS unit of time.
The C Street lights cycle from red to green only if the embedded car sensor indicates that a car is waiting. The lights cycle to yellow and then red as soon as no cars are waiting. Under no circumstances is the C Street green light to be lit for longer than a TL unit of time.

figure1

Date due: February 15, 2002
Report Requirements:

The Finite State Machine Diagram

Verilog Code

Simulation results of the schematic. You can use any Verilog Simulator for this - like Veriwell.

I cannot verify your downloaded design, but leave this for you to experiment with.

Optional Work (Not to be submitted):
This is the design of a Memory Controller for CPU to Memory Transactions. This FSM design could help in designing Bus Functional Models in Verilog or C. Bus Functional Models and Bus Interface Models are widely used in providing stimulus conforming to Bus Protocols for Design and Design Verification.

Design a memory controller finite state machine that implements a processor-memory handshake to the following specification. The processor initiates a transfer request by asserting REQ (request) while specifying a read or write (RW) operation. During a read operation (RW asserted), the processor waits for the memory controller to assert (data available). The processor can then sample the data. It unasserts the REQ line to end the memory cycle. During a write operation (RW unasserted), the processor drives data to the memory system, waiting for the memory controller to assert (write complete). When the processor sees this, it unasserts REQ to end the cycle.
The Moore state diagram for the memory controller is shown in Figure 1. Note that the read and write require multiple states for their execution. A timing diagram, showing the -relationships between the critical control signals for a read and a write cycle, is given in Figure 2. The state control signal -outputs are listed in Figure 3. Several of the memory controller's signals listed here are used to control the memory components. Their detailed meaning is not important, except that the appropriate signals should be asserted in the listed states.
figure2



figure3



figure4



The above problems are obtained from UC Berkeley website.