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Duncan M. (Hank) Walker
Professor and Graduate Advisor
Department of Computer Science
and Engineering
Texas A&M University
3112 TAMU
College Station, TX 77843-3112
Tel: (979) 862-4387 Fax: (979) 847-8578
Email: walker@cse.tamu.edu
Office: H. R. Bright Building 515B
Ph.D., Computer Science, Carnegie Mellon University, 1986
M.S., Computer Science, Carnegie Mellon University, 1984
B.S., Engineering (Honors), California Institute of Technology, 1979
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GRADUATE ADVISOR
Office:
Richardson 916C
Tel:
979-845-4087
Email: grad-advisor@cse.tamu.edu
Advising Hours (by appointment): Tue 2:00-4:00pm,
Wed 3:00-5:00pm
Advising
Assistant: Tina Broughton, Richardson 916E, 979-845-8981
Advising Fax:
979-862-3684
Important Links
Graduate Degree Programs –
includes FAQ, brochure and degree requirements
Graduate
Admissions FAQ – look here before asking admissions questions
Graduate
Program FAQ – look here before asking graduate program questions
Graduate
Program Brochure (pdf) – most details of CS graduate degrees
Office of Graduate
Studies – university-level graduate requirements, degree plans
International
Student Services – essential for international students
Registrar
– lots of information about registering for courses
RECENT TEACHING
Spring 2007: CPSC 614 Computer Architecture
Fall 2007: ENGR 111B Foundations of Engineering
I – Introduction to Electrical and Computer Engineering (on elearning)
Spring 2008: CPSC/ECEN 680 Testing and Diagnosis of
Digital Systems
Fall 2008: ENGR 111B Foundations of
Engineering I – Introduction to Electrical and Computer Engineering (on elearning)
Spring 2009: CPSC 312 Computer
Organization
Fall 2009: ENGR 111B Foundations of
Engineering I – Introduction to Electrical and Computer Engineering (on elearning)
Spring 2010: CSCE/ECEN 680 Testing and Diagnosis of
Digital Systems
RESEARCH INTERESTS (EDA Lab)
- Integrated Circuit Test
- Defect-Based Test
- Delay Test
- IDDQ Test
- Fault Diagnosis
- Realistic Fault Modeling
- Parametric and Functional
Yield Prediction
RECENT PROFESSIONAL EXPERIENCE
- Professor and Graduate
Advisor, Department of Computer Science, Texas A&M University,
2006-present
- Associate Professor,
Department of Computer Science, Texas A&M University; 1993-2006.
- Associate Head, Computing and
Facilities Services, Department of Computer Science, Texas A&M
University, 2000-2003.
- Academic Visitor, IBM Austin
Research Laboratory, 1997.
RECENT PROFESSIONAL ACTIVITIES AND
SERVICE
- Associate Editor, IEEE
Transactions on Computer-Aided Design of Circuits and Systems,
2010-present.
- Vice-General Chair, IEEE
International Workshop on Defect Based Testing, 2006.
- Program Committee, IEEE
International Conference on Computer Aided Design, 2003-2005.
- Program Committee, IEEE
International Workshop on Defect Based Testing, 2004-present.
SOME (OLDER) REPRESENTATIVE PUBLICATIONS
- H. Balachandran, Y. J. Kwon,
and D. M. H. Walker, "IDDQ Current Calibration with Process
Variations", IEEE Int’l Workshop on IDDQ Testing, Oct. 1995.
- B. Choi and D. M. H. Walker,
"Timing Analysis of Combinational Circuits Including Capacitive
Coupling and Statistical Process Variation", IEEE VLSI Test
Symposium, Montreal, Canada, April 2000. [PDF]
- J. Lee, D. M. H. Walker, L.
Milor, Y. Peng, and G. Hill, "IC Performance Prediction for Test Cost
Reduction", 1999 International Symposium on Semiconductor
Manufacturing, Santa Clara, CA, November 1999. [PDF]
- C. Lee and D. M. H. Walker,
"PROBE: A PPSFP Simulator for Resistive Bridging Faults", IEEE
VLSI Test Symposium, Montreal, Canada, April 2000. [PDF]
- Y. Liao and D. M. H. Walker,
"Optimal Voltage Testing for Physically-Based Faults", VLSI Test
Symp., Apr. 1996. [PDF]
- Y. Liao and D. M. H. Walker,
"Fault Coverage Analysis of Physically-Based Bridging Faults at
Different Power Supply Voltages", IEEE Int’l Test Conf., Oct. 1996. [PDF]
- G. M. Luong, and D. M. H.
Walker, "Test Generation for Global Delay Faults", IEEE Int’l
Test Conf., Oct. 1996, pp. 433-442. [PDF]
- D. Nayak and D. M. H.
Walker, "Simulation-Based Design Error Diagnosis and Correction in
Combinational Circuits", 1999 VLSI Test Symposium, Dana Point, CA,
April 1999, pp. 70-78. [PDF]
- V. Sar-Dessai and D. M. H.
Walker, "Accurate Fault Modeling and Fault Simulation of Resistive
Bridges", IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI
Systems", Nov. 1998. [PDF]
- V. Sar-Dessai, and D. M. H.
Walker, "Resistive Bridge Fault Modeling, Simulation, and Test
Generation", IEEE International Test Conference, September 1999. [PDF]
- T. A. Unni and D. M. H.
Walker, "Model-Based IDDQ Pass/Fail Limit Setting", 1998 IEEE
International Workshop on IDDQ Testing, San Jose, CA, November 1998.
- D. M. H. Walker,
"Requirements for Practical IDDQ Testing of Deep Submicron
Circuits", IEEE International Workshop on Current and Defect Based
Testing, Montreal, Canada, April 2000.
- L. Zhao, D. M. H. Walker,
and F. Lombardi, "Bridging Fault Detection in FPGA Interconnects
Using IDDQ", 1998 Sixth ACM International Symposium on
Field-Programmable Gate Arrays, Monterey, CA, March 1998, pp. 95-104.
- L. Zhao, D. M. H. Walker,
and F. Lombardi, "Detection of Bridging Faults in Logic Resources of
Configurable FPGAs Using IDDQ", IEEE International Test Conference,
Washington, DC, October 1998.
- L. Zhao, D. M. H. Walker,
and F. Lombardi, "IDDQ Testing of Bridging Faults in Logic Resources
of Reprogrammable Field Programmable Gate Arrays", IEEE Trans. on
Computers, October 1998, pp. 1136-1152.
- S. Balasubramaniam, A. K.
Sarwar and D.M.H. Walker. "Yield Learning in Integrated Circuit
Package Assembly", IEEE Trans. on Components, Packaging, and
Manufacturing, Technology, Part C: Manufacturing, pp. 133-141, April 1997.
- Z. Stanojevic, H.
Balachandran, D. M. H. Walker, F. Lakhani, S. Jandhyala, J. Saxena and K.
M. Butler, "Computer-Aided Fault to Defect Mapping (CAFDM) for Defect
Diagnosis", IEEE International Test Conference, Atlantic City, NJ,
October 2000. [PDF]
- Gaitonde, D.D., and D.M.H.
Walker, "Hierarchical Mapping of Spot Defects to Catastrophic Faults
Design and Applications," IEEE Trans. on Semiconductor Manufacturing,
pp. 167-177, May 1995.
- D. D. Gaitonde, J. Khare, D.
M. H. Walker and W. Maly "Estimation of Reject Rates in Testing of
Combinatorial Circuits", 1993 VLSI Test Symposium, Atlantic City, NJ,
April 1993, pp. 319-325. [PDF]
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